Dec 152017
 
From Cryix; allows you to view and modify internal register of 486DLC/SLC.
File CYRIX15.ZIP from The Programmer’s Corner in
Category Utilities for DOS and Windows Machines
From Cryix; allows you to view and modify internal register of 486DLC/SLC.
File Name File Size Zip Size Zip Type
CX486.CFG 200 97 deflated
CX486.EXE 70143 34054 deflated
CX486_CD.EXE 11209 6622 deflated
CX_DET.EXE 9355 5628 deflated
DMA_TST.EXE 36834 19062 deflated
README 12901 4010 deflated

Download File CYRIX15.ZIP Here

Contents of the README file



Cyrix Cx486SLC/DLC

****************************** UTILITIES **********************************

Using the Cx486SLC/DLC Utilities
----------------------------------------------------------------------------
This disk should contain the following files in the root directory
cx486.exe interactive cache control utility
cx486.cfg default cache settings .cfg file
cx_det.exe detects the Cx486SLC/DLC microprocessor
dma_tst.exe checks the dma cache coherency
cx486_cd.exe forces the CD and NW bits to 0 in BIOS'
that have incorrectly set these bits to 1.


DETECTING the Cx486SLC/DLC
----------------------------------------------------------------------------
To detect the Cx486SLC/DLC:
cx_det.exe

Note: The CX_DET.EXE program returns a 0 if the Intel part was found or
a 1 if the Cyrix part is found. The return values can be checked
in a batch file using the ERRORLEVEL batch file command.


VIEWING the STATUS of the Cx486SLC/DLC CONTROL REGISTERS
or
INTERACTIVELY CONTROLLING the Cx486SLC/DLC INTERNAL CACHE with CX486.EXE
---------------------------------------------------------------------------

To use the CX486.EXE utility from the command line type:
cx486.exe (set the path appropriately)

To get the CX486.EXE utility command line options type:
cx486.exe ? (set the path appropriately)
or
cx486.exe h

To automatically turn on the cache during boot using the CX486.CFG file
(or equialent) add the following line to the AUTOEXEC.BAT file:
cx486 q cx486.cfg (set the path appropriately)

*** READ APPENDIX A below on detailed information on the CX486.EXE ***
*** program and the CX486.CFG file! ***




TESTING CACHE COHERENCY using the DMA_TST.EXE PROGRAM
---------------------------------------------------------------------------
Note: The floppy drive is a DMA device that has the ability to modify
the contents of main memory without the cpu. CPUs that contain
internal memory caches must have a method to keep the internal
cache memory coherent with the external main memory. This is
usually accomplished by adding circuitry on the motherboard
to monitor when a DMA transfer takes place. The motherboard
DMA detection circuitry notifies the CPU when to invalidate
the contents of the internal cache by asserting the CPU FLSH#
pin.

The purpose of the DMA_TST.EXE program is to detect if a DMA transfer
can complete succesfully with guaranteed cache coherency. First, the
internal cache is configured automatically so that the FLSH# pin
is enabled. Second, the DMA_TST.EXE program will run the test.
Failures will reveal a cache coherency error which may result in
data corruption! If the CPU FLSH# pin is NOT connected to an
appropriate DMA detection circuit, the test will likely fail.


TO RUN the DMA Cache Coherency test, install a any diskette

1.) Setup the CONFIG.SYS and AUTOEXEC.BAT file as follows:
Preferred setup for the CONFIG.SYS file (DMA.BAT test ONLY)
files=20
buffers=20

Preferred setup for the AUTOEXEC.BAT file (DMA.BAT test ONLY)
prompt $p$g
path c:\dos

Note : ALL memory managers must be completely disabled in
the CONFIG.SYS FILE or this test will incorrectly display
a pass condition!!!

2.) Install any formatted diskette in drive A: and type:
dma_tst.exe (in the current directory)

To run the test "q"uickly and get a "Pass/Fail" answer type:
dma_tst.exe q

To get the DMA_TST.EXE utility command line options type:
dma_tst.exe ?
or
dma_tst.exe h

Note: The DMA_TST.EXE program returns a 0 if the test passes or a 1 if
the test fails. The return values can be checked in a batch file
using the ERRORLEVEL batch file command.


CLEARING the Cache Disable CD Bit in systems with misbehaved BIOS
---------------------------------------------------------------------------
Some systems have BIOS' that incorrectly set the Cache Disable "CD" bit.
Bits 30 and 29 of the 386 CR0 registers were reserved and should not
have been set by the BIOS. The CX486_CD.EXE program can be used on those
machines which have this misfortune in the BIOS. CX486_CD.EXE is intended
for DOS only and cannot be used in a DOS window in WINDOWS or OS/2. This
is due to the protected mode features of the operating system that does not
allow a program to update the CR0 register.

To run the CX486_CD.EXE program in the AUTOEXEC.BAT file "q"uickly type:
cx486_cd.exe q

To get command line information on how to use the CX486_CD.EXE utility
type:
cx486_cd.exe or cx486_cd.exe ?


****************************** APPENDIX A ***********************************

Notes about the CX486.CFG file

The CX486.CFG file is used by the CX486.EXE program to configure the cache
registers automatically according to the data contained in the CX486.CFG
file. Refer to the "CX486SLC/DLC Data Sheet" on the exact definitions
of the control registers. The CX486.EXE utility has screen sensitive
help which may assist you in configuring the cache.

The CX486.CFG file or equivalent can be created by the (F)ile Utilities
command in the CX486.EXE utility or edited using a text editor.
(Several *.CFG files are on this disk as examples.)

*** Editing the CX486.CFG file or equivalent: ***
CX486.EXE reads each line in this file looking for a matching
token(setup string) so it can convert the string into the value for
the appropriate register. The exact format of the file is:

Setup Strings (all values in HEX)
CC_0=03
CC_1=00
ARR_C4=00
ARR_C5=00
ARR_C6=00
ARR_C7=00
ARR_C8=00
ARR_C9=00
ARR_CA=00
ARR_CB=00
ARR_CC=00
ARR_CD=00
ARR_CE=00
ARR_CF=00

To edit the CX486.CFG file, look for the token(setup string) line
that matches the register to change/configure. Enter a HEX value
that appropriately sets up the register. You can edit the
value on the right side of the "=" sign, but you cannot edit/rename
the token(setup string) on the left side of the "=" sign.

Below are the bit definitions for the CX486SLC/DLC control registers:
.......................................................
Cache Configuration Register 0

Register 0C0h

Bit 0 - NC0: If = 1, sets the first 64K bytes at each 1M byte
boundary as non-cacheable, when operating in real or
virtual 8086 mode.
1 - NC1: If = 1, sets the 640K to 1M region as non-
cacheable.
2 - A20M: If = 1, enables A20M# input pin.
3 - KEN: If = 1, enables KEN# input pin.
4 - FLUSH: If = 1, enables KEN# input pin.
5 - BARB: If =, enables flushing of internal cache when
hold state is entered.
6 - C0: Selects cache organization:
0 = 2-way set associative
1 = directed mapped
7 - SUSPEND: If = 1, enables SUSP# input and SUSPA# output
pins.

setup string (value in HEX)
CC_0=1

.......................................................
Cache Configuration Register 1

Register 0C1h

Bit(0)= RPL: If = 1, enables output pins RPLSET and RPLVAL#. If
not enabled, outputs RPLSET and RPLVAL# wil float.
(1)= SMI: Enable SMM Pins. If=1, SMI# and SMADS# pins are enabled,
otherwise SMI# input is ignored and SMADS# will float.
(2)= SMAC: System Management Memory Access. If=1, accesses to SMM
memory space will be issued with SMADS# output active.
(3)= MMAC: Main Memory Access. If=1, all data accesses within a SMI
service routine will access main memory.
(4)= WP1: ARR1 0=Non-Cacheable Region, 1=Cacheable & Write Protected
(5)= WP2: ARR2 0=Non-Cacheable Region, 1=Cacheable & Write Protected
(6)= WP3: ARR3 0=Non-Cacheable Region, 1=Cacheable & Write Protected
(7)= SM4: Address Region 4 Control. If=1, Region 4 is Non-cacheable
SMM memory space, otherwise SMI# input is ignored.

setup string (value in HEX)
CC_1=0

.......................................................
Address Region Sizes:

For Reference:
0 = Disabled
1 = 4 Kbytes
2 = 8 Kbytes
3 = 16 Kbytes
4 = 32 Kbytes
5 = 64 Kbytes
6 = 128 Kbytes
7 = 256 Kbytes
8 = 512 Kbytes
9 = 1 Mbytes
0Ah = 2 Mbytes
0Bh = 4 Mbytes
0Ch = 8 Mbytes
0Dh = 16 Mbytes
0Eh = 32 Mbytes
0Fh = 4 Gbytes

NOTE: The "user input starting address" for the
Address Region Registers(ARR) should fall on a
boundary that coincides with the size of the
Address Region. CX486.EXE automatically translates
the starting address to the "effective starting address"

calculated by the Cx486SLC/DLC.

Example 1 (correct):
To setup a 640k (address A0000) to 1M (address 100000) region:

ARR1 start address: A0000 size: 128k (A0000 is on 128k boundary)
ARR2 start address: C0000 size: 256k (C0000 is on 256k boundary)

Example 2 (correct):
To setup a 512k (address 80000) to 1M (address 100000) region:

ARR1 start address: 80000 size: 512k (80000 is on 512k boundary)

.......................................................
Address Region 1

Register C4, C5, and C6

C4h
Bits 7-0 - Address bits A31 - A24 of Region 1 starting address

C5h
Bits 7-0 - Address bits A23 - A16 of Region 1 starting address

C6h
Bits 7-4 - Address bits A15 - A12 of Region 1 starting address
3-0 - Size of Address Region 1

setup strings (values in HEX)
ARR_C4=00
ARR_C5=0a
ARR_C6=06

.......................................................
Address Region 2

Register C7, C8 and C9h

C7h
Bits 7-0 - Address bits A31 - A24 of Region 2 starting address

C8h
Bits 7-0 - Address bits A23 - A16 of Region 2 starting address

C9h
Bits 7-4 - Address bits A15 - A12 of Region 2 starting address
3-0 - Size of Address Region 2

setup strings (values in HEX)
ARR_C7=00
ARR_C8=0c
ARR_C9=07

.......................................................
Address Region 3

Register CA, CB and CCh

CAh
Bits 7-0 - Address bits A31 - A24 of Region 3 starting address

CBh
Bits 7-0 - Address bits A23 - A16 of Region 3 starting address

CCh
Bits 7-4 - Address bits A15 - A12 of Region 3 starting address
3-0 - Size of Address Region 3

setup strings (values in HEX)
ARR_CA=00
ARR_CB=00
ARR_CC=00

.......................................................
Address Region 4

Register CD, CE and CFh

CDh
Bits 7-0 - Address bits A31 - A24 of Region 4 starting address

CEh
Bits 7-0 - Address bits A23 - A16 of Region 4 starting address

CFh
Bits 7-4 - Address bits A15 - A12 of Region 4 starting address
3-0 - Size of Address Region 4

setup strings (values in HEX)
ARR_CD=00
ARR_CE=00
ARR_CF=00

******************** APPENDIX B - PROGRAMMING EXAMPLES ********************

The programming examples supplied on this disk are ASSEMBLY language
routines. MAKE files are provided with debugging switches enabled for your
reference. Each example is under its respective directory.


TURNING ON the Cx486SLC/DLC INTERNAL CACHE - Example
----------------------------------------------------------------------------
do_cache.asm - example to enable the internal cache registers with a
640k to 1M non-cacheable region.


TURNING OFF the Cx486SLC/DLC INTERNAL CACHE - Example
----------------------------------------------------------------------------
no_cache.asm - example to return to internal cache registers
to the reset state.


DETECTING the Cx486SLC/DLC
----------------------------------------------------------------------------
cx_det.c - C code driver program for detect.asm
detect.asm - example to detect the Cx486SLC/DLC using
the undefined arithmetic flags after a
divide instruction.


CX486.EXE REVSION STATUS:
----------------------------
rev 1.0 - ported code from m5 utility
----------------------------
rev 1.1 - added more command line control
----------------------------
rev 1.2 - edited text
1.21- fixed paging bit
1.22- added compatibility with m5.cfg file format.
1.23- fixed out of range values in do_edit
----------------------------



 December 15, 2017  Add comments

Leave a Reply