Category : Tutorials + Patches
Archive   : NAT_UART.ZIP
Filename : REGS.H

 
Output of file : REGS.H contained in archive : NAT_UART.ZIP
/* REGISTER.H -- register I/O header file
*
* Greg DeJager 7/18/89
*
*
*/

/* UART base address (COM2 used for now)*/
#define ubase 0x2f8

/* UART register definitions using UART base address */
#define RBR (ubase+0) /* Receive Buffer Register (R )(DLAB==0)*/
#define THR (ubase+0) /* Transmitter Holding Reg ( W)(DLAB==0)*/
#define IER (ubase+1) /* Interrupt Enable Register (R/W)(DLAB==0)*/
#define IIR (ubase+2) /* Interrupt Ident. Register (R ) */
#define FCR (ubase+2) /* FIFO Control Register (W ) */
#define LCR (ubase+3) /* Line Control Register (R/W) */
#define MCR (ubase+4) /* MODEM Control Register (R/W) */
#define LSR (ubase+5) /* Line Status Register (R ) */
#define MSR (ubase+6) /* MODEM Status Register (R/W) */
#define SCR (ubase+7) /* SCratch Register (R/W) */
#define DLL (ubase+0) /* Divisor Latch (LSB) (R/W)(DLAB==1)*/
#define DLM (ubase+1) /* Divisor Latch (MSB) (R/W)(DLAB==1)*/


/* DMA Controller Extended Mode register definitions */
#define FR 0x18 /* Function Register */
#define EFR 0x1a /* Execute Function Register */


/* bit settings */
/* 16550 IIR */
#define F_NOIP 0xC1 /* NO Interrupt Pending */
#define F_RLST 0xC6 /* Receiver Line STatus interrupt */
#define F_RDAV 0xC4 /* Received Data AVailable */
#define F_IIR_THRE 0xC2 /* Transmitter Holding Register Empty */
#define F_CHR_TIMEOUT 0xCC /* Receiver FIFO Timeout interrupt */


/* LSR and MSR: */
#define DR 1 /* bit 0: Data Ready */
#define OE 2 /* bit 1: Overrun Error */
#define PE 4 /* bit 2: Parity Error */
#define FE 8 /* bit 3: Framing Error */
#define BI 0x10 /* bit 4: Break Interrupt */
#define LSR_THRE 0x20 /* bit 5: Transmtr Holding Reg Empty */
#define TEMT 0x40 /* bit 6: Transmitter Empty */
#define CTS 0x10 /* bit 4: Clear To Send */

/* values for writing to IER */
#define IER_VAL1 0x05 /* RDA & RLS */
#define IER_VAL2 0x07 /* RDA & THRE & RLS */

/* values for writing to MCR */
#define OUT2 0x08

/* values for writing to FCR */
#define CLR_FIFO 0x06 /* Clear Rx and Tx FIFOs */
#define FIFO_EN 0xC1 /* Enable FIFOs, set trigger to 14 */

/* data error ID numbers */
#define ENDPROG 1 /* keyboard hit */
#define FALSEINT 2 /* CPU int with IIR = 1 */
#define STATUSERR 3 /* Line Status Interrupt */
#define MISMATCH 4 /* Data mismatch */
#define RX_ERROR 5 /* RDAI with no DR indication */
#define TX_ERROR 6 /* THREI with no THRE indication */
#define IIR_ERROR 7 /* invalid IIR code */
#define TIMEOUT 8 /* Receiver FIFO Timeout Interrupt */
#define TIMEOUT_ERR 9 /* False Receiver FIFO Timeout */

/* macros */
#define rdIIR() ((UCHAR)inp(IIR)) /* read IIR */
#define rdLSR() ((UCHAR)inp(LSR)) /* read LSR */
#define rdMSR() ((UCHAR)inp(MSR)) /* read MSR */
#define rdRBR() ((UCHAR)inp(RBR)) /* read RBR */
#define wrTHR(val) (outp(THR, val)) /* write THR */
#define wrIER(val) (outp(IER, val)) /* write IER */
#define wrLCR(val) (outp(LCR, val)) /* write LCR */
#define wrMCR(val) (outp(MCR, val)) /* write MCR */
#define wrFCR(val) (outp(FCR, val)) /* write FCR */
#define wrFR(val) (outp(FR, val)) /* write FR */
#define wrEFR(val) (outp(EFR, val)) /* write EFR */
#define rdEFR() ((UCHAR)inp(IIR)) /* read EFR */


/* end of serio.h */


  3 Responses to “Category : Tutorials + Patches
Archive   : NAT_UART.ZIP
Filename : REGS.H

  1. Very nice! Thank you for this wonderful archive. I wonder why I found it only now. Long live the BBS file archives!

  2. This is so awesome! 😀 I’d be cool if you could download an entire archive of this at once, though.

  3. But one thing that puzzles me is the “mtswslnkmcjklsdlsbdmMICROSOFT” string. There is an article about it here. It is definitely worth a read: http://www.os2museum.com/wp/mtswslnk/