Programming the 8251A USART


Prior to starting data transmission or reception, the 8251A must be loaded
with a set of control words generated by the CPU via the OUT instruction.
These control signals define the complete functional definition of the 8251A
and must immediately follow a reset operation (internal reset, or external).

The control words are split up into two formats:

1. Mode instruction
2. Command instruction

Mode instruction


This instruction defines the general operational characteristics of the 8251A.
It must follow an internal or external reset operation. Once the mode
instruction has been written into the 8251A by the CPU, Command instructions
may then be written.

The mode instruction format:

BIT 7 6 5 4 3 2 1 0
Baud rate factor

0 1 0 1

0 0 1 1

SYNC x1 x16 x64
MODE


Character Length

0 1 0 1

0 0 1 1

5 6 7 8
BIT BIT BIT BIT


Parity enable.
Even parity generation check.

Number of stop bits

0 1 0 1

0 0 1 1

INVALID 1 1 2
BIT BIT BIT




Command instruction


This instruction defines a word that is used to control the actual operation
of the 8251A. Both the mode and the command instructions must conform to a
specified sequence for proper operation.

1. Mode instruction.
2. Command instruction.

The mode instruction must be written immediately following a reset operation,
prior to using the 8251A for data communication.

All control words written into the 8251A after the mode instruction will load
the command instruction. Command instructions can be written into the 8251A
at any time during data communication. To return to the mode instruction
format, the master reset bit in the command instruction word can be set
to initiate an internal reset operation which automatically places the 8251A
back into the mode instruction format. Command instructions must follow the
mode instructions.

Once the functional definition of the 8251A has been programmed by the mode
instruction, then the device is ready for data communication. The command
instruction controls the actual operation of the selected format. Functions
such as: Enable transmit/recieve, error reset, and modem controls are
provided by the command instruction.

Once the mode instruction has been written into the 8251A, then all further
writes to the chip will load a command instruction. An internal or external
reset operation will return the 8251A to the Mode instruction format.

Note: Internal reset on power-up

When power is first applied, the 8251A may come up in the mode, Sync, or
command format. To guarantee that the device is in the command instruction
format before the reset command is issued, it is safest to execute the
worst-case initialization sequence, loading three dummy characters, probably
ones that will not affect the signal lines should be sent. This insures
that the device will be ready to accept a command instuction. An internal
reset command (IR) should then be sent, thus returning the 8251A to the
"idle" state, ready to accept a mode instruction.


Command instruction format:

BIT 7 6 5 4 3 2 1 0

Transmit enable.
Data terminal ready.
Recieve enable.
Send break character.
Error reset.
Request to send.
Internal reset.
Enter Hunt mode (has no effect in async mode).


Status read


In data communications it is often necessary to examine the "status" of the
active device to ascertain it errors have occurred or other conditions that
require the processor's attention. The 8251A has facilities that allow the
programmer to "read" the status of the device at any time during the functional
operation (Status update is inhibited during status read).

Some bits in the status read format have identical meanings to the external
output pins so that the 8251A can be used in a completely polled or interrupt-
driven environment. TxRDY is an exception.

Note that the status update can have a maximum delay of 28 clock periods
from the actual event affecting the status.

Status read format:

BIT 7 6 5 4 3 2 1 0

TxRDY.
RxRDY.
TxEMPTY.
Parity error.
Overrun error.
Framing error.
Break detect.
Data set ready.