Category : Miscellaneous Language Source Code
Archive : NEC-V20.ZIP
Filename : VINTRO.000
Output of file : VINTRO.000 contained in archive : NEC-V20.ZIP
P¸ Pèaflags are affected.±PèÀaè }¹] èK_¸ P¸ P¸ PèPaDImmediate applications are also the same as for the INS instruction.±Pè^aè½|¹] èé^¸ P¸ P¸ Pèî`2Next... Packed BCD data processing instructions...±Pèaèm|¹ è^èGh PCè½}é å]à è5`Á¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe following instructions are all part of a set that NEC has implemented±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLinto the V20 and V30 to give the programmer tools to manipulate Packed BCD±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLdata either as strings or byte-format operands. Packed BCD data is used in±PèTdè³¹] èßa¸ P¸ P¸ PèäcLbusiness applications that require numerical accuracy of a higher order than±PèêcèI¹] èua¸ P¸ P¸ PèzcLthat available with real number math. For example, Turbo Pascal is available±Pècèß~¹] è a¸ P¸ P¸ PècIin a Turbo BCD Pascal version for those specific types of applications...±Pècèx~¹] è¤`¸ P¸ P¸ Pè©bLThe first instruction in this set is the ADD4S instruction. This instruction±Pè¯bè~¹] è:`¸ P¸ P¸ Pè?bLadds two BCD strings and stores the result in the location of the second BCD±PèEbè¤}¹] èÐ_¸ P¸
P¸ PèÕaLstring. The format of the instruction is very simple : ADD4S (no operands)±PèÛaè:}¹] èf_¸ P¸ P¸ PèkaLThe programmer must set up the IX index register to point to the first BCD±PèqaèÐ|¹] èü^¸ P¸ P¸ PèaLstring, and the IY register to the second BCD string. The ADD4S instruction±Pèaèf|¹] è^¸ P¸
P¸ Pè`Lis then executed and the result is placed in the location referenced by the±Pè`èü{¹] è(^¸ P¸ P¸ Pè-`LIY register, replacing the second operand. The length of the strings must be±Pè3`è{¹] è¾]¸ P¸ P¸ PèÃ_Ithe same, and must be placed in the CL register. The opcode for ADD4S is:±PèÌ_è+{¹] èW]¸ P¸ P¸ Pè\_F Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pèh_èÇz¹] èó\¸ P¸ P¸ Pèø^G --------------------------------------------------------------------±Pè_èbz¹] è\¸ P¸ P¸ Pè^F 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0±Pè^èþy¹] è*\¸ P¸ P¸ Pè/^LThe instruction takes ((19*(CL/2))+7) clocks to execute, and the V, CY and Z±Pè5^èy¹] èÀ[¸ P¸ P¸ PèÅ]flags may be affected.±Pè^è`y¹ è[è:e PCè°zé å]à è5`¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe SUB4S instruction works EXACTLY like the ADD4S instruction except that±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLit subtracts the string addressed by the IX register from that addressed by±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLthe IY register, and places the result where the IY register points to. The±PèTdè³¹] èßa¸ P¸ P¸ Pèäcopcode for SUB4S is:±Pè"dè¹] èa¸ P¸ P¸ Pè²cF Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pè¾cè ¹] èIa¸ P¸ P¸ PèNcG --------------------------------------------------------------------±PèYcè¸~¹] èä`¸ P¸ P¸ PèébF 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0±PèõbèT~¹] è`¸ P¸
P¸ Pè bLThe instruction takes ((19*(CL/2))+7) clocks to execute, and the V, CY and Z±Pèbèê}¹] è`¸ P¸ P¸ Pèbflags may be affected.±PèWbè¶}¹] èâ_¸ P¸
P¸ PèçaLThe CMP4S instruction performs the same operation as SUB4S, but it does not±PèíaèL}¹] èx_¸ P¸ P¸ Pè}aEreplace the string addressed by IY register. The opcode for CMP4S is:±Pèaèé|¹] è_¸ P¸ P¸ PèaF Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pè&aè |¹] è±^¸ P¸ P¸ Pè¶`G --------------------------------------------------------------------±PèÁ`è |¹] èL^¸ P¸ P¸ PèQ`F 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0±Pè]`è¼{¹] èè]¸ P¸ P¸ Pèí_LThe instruction takes ((19*(CL/2))+7) clocks to execute, and the V, CY and Z±Pèó_èR{¹] è~]¸ P¸ P¸ Pè_flags may be affected.±Pè¿_è {¹ èJ]èøf PCèn|é å]à è5`¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe ROL4 and ROR4 instructions allow you to manipulate byte-format BCD data±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLby rotating it one digit to the left or to the right, depending on which one±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLyou decide to use. The lower 4 bits of the AL register is used for as a temp±PèTdè³¹] èßa¸ P¸ P¸ PèäcLwork area to accomplish this, and the operand can be either a register or a±PèêcèI¹] èua¸ P¸ P¸ Pèzc4memory location. The format of the instructions are:±Pècè÷~¹] è#a¸ P¸ P¸ Pè(c? ROL4 reg8 or ROL4 mem8 - ROR4 reg8 or ROR4 mem8±Pè;cè~¹] èÆ`¸ P¸ P¸ PèËb%Opcodes for the ROL4 instruction are:±PèøbèW~¹] è`¸ P¸ P¸ PèbL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pèbèí}¹] è`¸ P¸ P¸ Pè bL -------------------------------------------------------------------±Pè$bè}¹] è¯_¸ P¸
P¸ Pè´aLreg8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0±Pèºaè}¹] èE_¸ P¸ P¸ PèJaL 1 1 0 0 0 [ reg ] - - - - - - - -±PèPaè¯|¹] èÛ^¸ P¸ P¸ Pèà`Lmem8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0±Pèæ`èE|¹] èq^¸ P¸ P¸ Pèv`L [ mod ] 0 0 0 [ reg ] - - - - - - - -±Pè|`èÛ{¹] è^¸ P¸ P¸ Pè `LThe instruction takes 25 clocks to execute if rotating a register, 28 if it±Pè`èq{¹] è]¸ P¸ P¸ Pè¢_Bis rotating a memory byte. No flags are affected by its execution.±Pè²_è{¹ è=]èëf PCèa|é å]à è5`½¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"e)The opcodes for the ROR4 instruction are:±PèKe誹] èÖb¸ P¸ P¸ PèÛdL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pèádè@¹] èlb¸ P¸ P¸ PèqdL -------------------------------------------------------------------±PèwdèÖ¹] èb¸ P¸ P¸ PèdLreg8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0±Pè
dèl¹] èa¸ P¸ P¸ PècL 1 1 0 0 0 [ reg ] - - - - - - - -±Pè£cè¹] è.a¸ P¸ P¸ Pè3cLmem8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0±Pè9cè~¹] èÄ`¸ P¸ P¸ PèÉbL [ mod ] 0 0 0 [ reg ] - - - - - - - -±PèÏbè.~¹] èZ`¸ P¸
P¸ Pè_bLThe instruction takes 29 clocks to execute if rotating a register, 33 if it±PèebèÄ}¹] èð_¸ P¸ P¸ PèõaBis rotating a memory byte. No flags are affected by its execution.±Pèbèd}¹ è_è>i PCè´~é å]à è5`Ö¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe next set of instructions is the bit manipulation group. NEC has added 4±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLnew instructions which are normally available in other CPUs but are not part±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLof the 8088/86 instruction set. These instructions allow us to manipulate±PèTdè³¹] èßa¸ P¸ P¸ PèäcLdistinct bits in memory, something which I know many of us programmers wish±PèêcèI¹] èua¸ P¸ P¸ PèzcLwe had in the 8088/86s. There are four instructions in this group. They are:±Pècèß~¹] è a¸ P¸ P¸ Pèc3 TEST1 - NOT1 - CLR1 - SET1±Pè/cè~¹] èº`¸ P¸
P¸ Pè¿bLAll of these instructions can use 8- or 16-bit registers and 8- or 16-bit±PèÅbè$~¹] èP`¸ P¸ P¸ PèUbLarguments as operands, and in each one the contents of the CL register tells±Pè[bèº}¹] èæ_¸ P¸ P¸ PèëaLthe processor exactly which bit within that argument we want to perform an±PèñaèP}¹] è|_¸ P¸ P¸ PèaLoperation on. An immediate data argument of 3 or 4 bits can also be used to±Pèaèæ|¹] è_¸ P¸ P¸ PèaLspecify the bit offset we want to work on. So, lets look at the first one in±Pè aè||¹] è¨^¸ P¸ P¸ Pè`the group, TEST1...±Pèì`èK|¹ èw^è%h PCè}é å]à è5` ¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe TEST1 instruction tests a specific bit in a register or memory location.±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLIf the bit is 1, the Z flag is reset to 0. If the bit is 0, the Z flag is±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLreset to 1. The first operand can be a 8- or 16-bit register or an 8- or 16-±PèTdè³¹] èßa¸ P¸ P¸ PèäcLbit memory location. The bit offset can be specified by CL or by a 3- or 4-±PèêcèI¹] èua¸ P¸ P¸ PèzcLbit immediate data operand. The 2nd and 3rd (1st is always 0Fh) opcodes are:±Pècèß~¹] è a¸ P¸ P¸ PècI Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pècèx~¹] è¤`¸ P¸ P¸ Pè©bL ----------------------------------------------------------------------±Pè¯bè~¹] è:`¸ P¸ P¸ Pè?bIreg8,CL 0 0 0 1 0 0 0 0 1 1 0 0 0 [ reg ]±PèHbè§}¹] èÓ_¸ P¸
P¸ PèØaIreg16,CL 0 0 0 1 0 0 0 0 [ mod ] 0 0 0 [ mem ]±Pèáaè@}¹] èl_¸ P¸ P¸ PèqaImem8,CL 0 0 0 1 0 0 0 1 1 1 0 0 0 [ reg ]±PèzaèÙ|¹] è_¸ P¸ P¸ Pè
aImem16,CL 0 0 0 1 0 0 0 1 [ mod ] 0 0 0 [ mem ]±Pèaèr|¹] è^¸ P¸
P¸ Pè£`Ireg8,imm3 0 0 0 1 1 0 0 0 1 1 0 0 0 [ reg ]±Pè¬`è |¹] è7^¸ P¸ P¸ Pè<`Ireg16,imm4 0 0 0 1 1 0 0 0 [ mod ] 0 0 0 [ mem ]±PèE`è¤{¹] èÐ]¸ P¸ P¸ PèÕ_Imem8,imm3 0 0 0 1 1 0 0 1 1 1 0 0 0 [ reg ]±PèÞ_è={¹] èi]¸ P¸ P¸ Pèn_Imem16,imm4 0 0 0 1 1 0 0 1 [ mod ] 0 0 0 [ mem ]±Pèw_èÖz¹] è]¸ P¸ P¸ Pè_LClocks for each are 3, 12, 3, 12-16, 4, 13, 4, 13-17 respectively, Z flag is±Pè
_èlz¹] è\¸ P¸ P¸ Pè^8flag is affected, and the P and S flags may be affected.±Pè·^èz¹ èB\èðe PCèf{é å]à è5`ͬUìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe NOT1 instruction inverts a specific bit in a register or mem location.±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLThe first operand can be a 8- or 16-bit register or an 8- or 16-bit memory±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLlocation. The bit offset can be specified by CL or by a 3- or 4-bit±PèTdè³¹] èßa¸ P¸ P¸ PèäcHimmediate data operand. The 2nd and 3rd (1st is always 0Fh) opcodes are:±PèîcèM¹] èya¸ P¸ P¸ Pè~cI Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pècèæ~¹] èa¸ P¸ P¸ PècL ----------------------------------------------------------------------±Pè cè|~¹] è¨`¸ P¸ P¸ PèbIreg8,CL 0 0 0 1 0 1 1 0 1 1 0 0 0 [ reg ]±Pè¶bè~¹] èA`¸ P¸ P¸ PèFbIreg16,CL 0 0 0 1 0 1 1 0 [ mod ] 0 0 0 [ mem ]±PèObè®}¹] èÚ_¸ P¸
P¸ PèßaImem8,CL 0 0 0 1 0 1 1 1 1 1 0 0 0 [ reg ]±PèèaèG}¹] ès_¸ P¸ P¸ PèxaImem16,CL 0 0 0 1 0 1 1 1 [ mod ] 0 0 0 [ mem ]±Pèaèà|¹] è _¸ P¸ P¸ PèaIreg8,imm3 0 0 0 1 1 1 1 0 1 1 0 0 0 [ reg ]±Pèaèy|¹] è¥^¸ P¸
P¸ Pèª`Ireg16,imm4 0 0 0 1 1 1 1 0 [ mod ] 0 0 0 [ mem ]±Pè³`è|¹] è>^¸ P¸ P¸ PèC`Imem8,imm3 0 0 0 1 1 1 1 1 1 1 0 0 0 [ reg ]±PèL`è«{¹] è×]¸ P¸ P¸ PèÜ_Imem16,imm4 0 0 0 1 1 1 1 1 [ mod ] 0 0 0 [ mem ]±Pèå_èD{¹] èp]¸ P¸ P¸ Pèu_ICY 1 1 1 1 0 1 0 1 - - - - - - - -±Pè~_èÝz¹] è ]¸ P¸ P¸ Pè_LClocks for each are 4, 18, 4, 18-26, 5, 19, 5, 19-27 respectively, and no±Pè_èsz¹] è\¸ P¸ P¸ Pè¤^Lflags are affected. The last one is an extra operand. If CY is used as the±Pèª^è z¹] è5\¸ P¸ P¸ Pè:^LONLY operand, the CY flag is inverted. You use ONE opcode for this last one.±Pè@^èy¹] èË[¸ P¸ P¸ PèÐ]-This last operation takes 1 clock to execute.±Pèõ]èTy¹ è[è.e PCè¤zé å]à è5`9¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe CLR1 instruction clears a specific bit in a register or mem location.±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLThe first operand can be a 8- or 16-bit register or an 8- or 16-bit memory±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLlocation. The bit offset can be specified by CL or by a 3- or 4-bit±PèTdè³¹] èßa¸ P¸ P¸ PèäcHimmediate data operand. The 2nd and 3rd (1st is always 0Fh) opcodes are:±PèîcèM¹] èya¸ P¸ P¸ Pè~cI Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pècèæ~¹] èa¸ P¸ P¸ PècL ----------------------------------------------------------------------±Pè cè|~¹] è¨`¸ P¸ P¸ PèbIreg8,CL 0 0 0 1 0 0 1 0 1 1 0 0 0 [ reg ]±Pè¶bè~¹] èA`¸ P¸ P¸ PèFbIreg16,CL 0 0 0 1 0 0 1 0 [ mod ] 0 0 0 [ mem ]±PèObè®}¹] èÚ_¸ P¸
P¸ PèßaImem8,CL 0 0 0 1 0 0 1 1 1 1 0 0 0 [ reg ]±PèèaèG}¹] ès_¸ P¸ P¸ PèxaImem16,CL 0 0 0 1 0 0 1 1 [ mod ] 0 0 0 [ mem ]±Pèaèà|¹] è _¸ P¸ P¸ PèaIreg8,imm3 0 0 0 1 1 0 1 0 1 1 0 0 0 [ reg ]±Pèaèy|¹] è¥^¸ P¸
P¸ Pèª`Ireg16,imm4 0 0 0 1 1 0 1 0 [ mod ] 0 0 0 [ mem ]±Pè³`è|¹] è>^¸ P¸ P¸ PèC`Imem8,imm3 0 0 0 1 1 0 1 1 1 1 0 0 0 [ reg ]±PèL`è«{¹] è×]¸ P¸ P¸ PèÜ_Imem16,imm4 0 0 0 1 1 0 1 1 [ mod ] 0 0 0 [ mem ]±Pèå_èD{¹] èp]¸ P¸ P¸ Pèu_ICY 1 1 1 1 1 0 0 0 - - - - - - - -±Pè~_èÝz¹] è ]¸ P¸ P¸ Pè_IDIR 1 1 1 1 1 1 0 0 - - - - - - - -±Pè_èvz¹] è¢\¸ P¸ P¸ Pè§^LClocks for each are 5, 14, 5, 14-22, 6, 15, 6, 15-27 respectively, and no±Pè^è z¹] è8\¸ P¸ P¸ Pè=^Lflags are affected. The last two are extra operands. If CY or DIR is used±PèC^è¢y¹] èÎ[¸ P¸ P¸ PèÓ]Las the operand, it will be inverted. You use ONE opcode for these last two±PèÙ]è8y¹] èd[¸ P¸ P¸ Pèi]2instructions. They take 2 clock cycles to execute.±Pè]èèx¹ è[èÂd PCè8zé å]à è5`9¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe SET1 instruction sets a specific bit in a register or mem location.±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLThe first operand can be a 8- or 16-bit register or an 8- or 16-bit memory±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLlocation. The bit offset can be specified by CL or by a 3- or 4-bit±PèTdè³¹] èßa¸ P¸ P¸ PèäcHimmediate data operand. The 2nd and 3rd (1st is always 0Fh) opcodes are:±PèîcèM¹] èya¸ P¸ P¸ Pè~cI Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pècèæ~¹] èa¸ P¸ P¸ PècL ----------------------------------------------------------------------±Pè cè|~¹] è¨`¸ P¸ P¸ PèbIreg8,CL 0 0 0 1 0 1 0 0 1 1 0 0 0 [ reg ]±Pè¶bè~¹] èA`¸ P¸ P¸ PèFbIreg16,CL 0 0 0 1 0 1 0 0 [ mod ] 0 0 0 [ mem ]±PèObè®}¹] èÚ_¸ P¸
P¸ PèßaImem8,CL 0 0 0 1 0 1 0 1 1 1 0 0 0 [ reg ]±PèèaèG}¹] ès_¸ P¸ P¸ PèxaImem16,CL 0 0 0 1 0 1 0 1 [ mod ] 0 0 0 [ mem ]±Pèaèà|¹] è _¸ P¸ P¸ PèaIreg8,imm3 0 0 0 1 1 1 0 0 1 1 0 0 0 [ reg ]±Pèaèy|¹] è¥^¸ P¸
P¸ Pèª`Ireg16,imm4 0 0 0 1 1 1 0 0 [ mod ] 0 0 0 [ mem ]±Pè³`è|¹] è>^¸ P¸ P¸ PèC`Imem8,imm3 0 0 0 1 1 1 0 1 1 1 0 0 0 [ reg ]±PèL`è«{¹] è×]¸ P¸ P¸ PèÜ_Imem16,imm4 0 0 0 1 1 1 0 1 [ mod ] 0 0 0 [ mem ]±Pèå_èD{¹] èp]¸ P¸ P¸ Pèu_ICY 1 1 1 1 1 0 0 1 - - - - - - - -±Pè~_èÝz¹] è ]¸ P¸ P¸ Pè_IDIR 1 1 1 1 1 1 0 1 - - - - - - - -±Pè_èvz¹] è¢\¸ P¸ P¸ Pè§^LClocks for each are 4, 13, 4, 13-21, 5, 14, 5, 14-22 respectively, and no±Pè^è z¹] è8\¸ P¸ P¸ Pè=^Lflags are affected. The last two are extra operands. If CY or DIR is used±PèC^è¢y¹] èÎ[¸ P¸ P¸ PèÓ]Las the operand, it will be set. You use ONE opcode for these last two±PèÙ]è8y¹] èd[¸ P¸ P¸ Pèi]2instructions. They take 2 clock cycles to execute.±Pè]èèx¹ è[èÂd PCè8zé å]à è5`¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe REPC instruction is used to facilitate mass-transfer block operations by±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLsetting up repetition of a block transfer instruction based on the current±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLvalue of the CY flag. The primitive block transfer instruction following the±PèTdè³¹] èßa¸ P¸ P¸ PèäcDREPC instruction will continue to execute as long as CY is set to 1.±PèòcèQ¹] è}a¸ P¸ P¸ PècLThe REPNC instruction works in the opposite manner, with the primitive block±Pècèç~¹] èa¸ P¸ P¸ PècLtransfer instructions following the instruction continuing to repeat as long±Pè cè}~¹] è©`¸ P¸ P¸ Pè®bCas CY remains cleared to 0. The opcodes for these instructions are:±Pè½bè ~¹] èH`¸ P¸
P¸ PèMbI Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±PèVbèµ}¹] èá_¸ P¸ P¸ PèæaL ----------------------------------------------------------------------±PèìaèK}¹] èw_¸ P¸ P¸ Pè|aIREPC 0 1 1 0 0 1 0 1 - - - - - - - -±Pè aèä|¹] è_¸ P¸
P¸ PèaIREPNC 0 1 1 0 0 1 0 0 - - - - - - - -±Pè aè}|¹] è©^¸ P¸ P¸ Pè®`LBoth of these instructions require two clocks to execute, and no flags are±Pè´`è|¹] è?^¸ P¸ P¸ PèD` modified.±Pè`èì{¹] è^¸ P¸ P¸ Pè `LAnd now... what I think a few people have been waiting for. The V20/V30 CPUs±Pè#`è{¹] è®]¸ P¸ P¸ Pè³_Jcan operate in two modes, native and 8080 emulation... Lets take a look...±Pè»_è{¹ èF]èôf PCèj|é å]à è5`O¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe V20 and V30 have two operating modes. One is called NATIVE mode, and±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLthe other is called EMULATION mode. When the device is in the NATIVE mode it±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLexecutes all the incoming instructions as 8088/86/188/186, enhanced, or±PèTdè³¹] èßa¸ P¸ P¸ PèäcLunique instructions. When the device is set to emulation mode, it interprets±PèêcèI¹] èua¸ P¸ P¸ PèzcLall incoming instructions as Intel 8080 instructions, supporting the entire±Pècèß~¹] è a¸ P¸
P¸ PècLinstruction set of that microprocessor. A special flag, the MODE flag, is±Pècèu~¹] è¡`¸ P¸ P¸ Pè¦bLthe one that is used to determine which mode the processor is in. The native±Pè¬bè ~¹] è7`¸ P¸ P¸ Pè
P¸ Pèèa: --------- -----±Pè bè_}¹] è_¸ P¸ P¸ Pèa? 8080 V20/V30 8080 V20/V30 8080 V20/V30±Pè£aè}¹] è._¸ P¸ P¸ Pè3a? ---- ------- ---- ------- ---- -------±PèFaè¥|¹] èÑ^¸ P¸
P¸ PèÖ`= A AL H BH C CY±Pèë`èJ|¹] èv^¸ P¸ P¸ Pè{`< B CH L BL Z Z±Pè`èð{¹] è ^¸ P¸ P¸ Pè!`< C CL SP BP S S±Pè7`è{¹] èÂ]¸ P¸ P¸ PèÇ_< D DH PC PC P P±PèÝ_è<{¹] èh]¸ P¸ P¸ Pèm_= E DL AC AC±Pè_èáz¹] è
]¸ P¸ P¸ Pè_LIn the native mode SP is used as the stack pointer, and in emulation mode BP±Pè_èwz¹] è£\¸ P¸ P¸ Pè¨^Lperforms this function. This prevents the stack of one mode from being±Pè®^è
z¹] è9\¸ P¸ P¸ Pè>^=destroyed by the other when switching between modes. Smart...±PèS^è²y¹ èÞ[èe PCè{é å]à è5`¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThe SP, IX, IY and AH registers and the four segment registers PS, SS, DS0,±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLand DS1 used in the native mode are not affected by operations in the 8080±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLemulation mode. In the 8080 emulations mode, the code segment is set by the±PèTdè³¹] èßa¸ P¸ P¸ PèäcLPS register (which is set automatically by the interrupt vector), and the±PèêcèI¹] èua¸ P¸ P¸ PèzcLdata segment is determined by the DS0 register (which must be set by the±Pècèß~¹] è a¸ P¸ P¸ PècLprogrammer immediately before entering 8080 emulation mode). The opcodes for±Pècèu~¹] è¡`¸ P¸ P¸ Pè¦b%the BRKEM instruction are as follows:±PèÓbè2~¹] è^`¸ P¸ P¸ PècbI Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±PèlbèË}¹] è÷_¸ P¸
P¸ PèüaL ----------------------------------------------------------------------±Pèbèa}¹] è_¸ P¸ P¸ PèaIimm8 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1±Pèaèú|¹] è&_¸ P¸
P¸ Pè+aLThe instruction takes 38 to 58 clocks to execute, and modifies no flags by±Pè1aè|¹] è¼^¸ P¸ P¸ PèÁ`+itself, since it saves them onto the stack.±Pèè`èG|¹] ès^¸ P¸ P¸ Pèx`LSo, as you can see, it is relatively simple to enter into 8080 emulation. It±Pè~`èÝ{¹] è ^¸ P¸ P¸ Pè`Lis a simple interrupt service routine call with some setup involved. Now,±Pè`ès{¹] è]¸ P¸ P¸ Pè¤_5the question is, how do we get out of the 8080 mode??±PèÁ_è {¹ èL]èúf PCèp|é å]à è5`¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLTo get back from emulation mode into native mode, the RETEM instruction is±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLused, with no operands. Note that this instruction is executed while in 8080±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLemulation mode, and is interpreted as such. When it is executed, the CPU±PèTdè³¹] èßa¸ P¸ P¸ PèäcLrestores the PS, PC and PSW registers (just like it would if it had returned±PèêcèI¹] èua¸ P¸ P¸ PèzcLfrom a normal interrupt service routine), and, since the value of the MODE±Pècèß~¹] è a¸ P¸ P¸ PècFflag was a 1 when the flags were saved, it goes back into native mode.±Pè cè{~¹] è§`¸ P¸ P¸ Pè¬b5The opcodes for the RETEM instruction are as follows:±PèÉbè(~¹] èT`¸ P¸ P¸ PèYbF Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±PèebèÄ}¹] èð_¸ P¸
P¸ PèõaI ----------------------------------------------------------------------±Pèþaè]}¹] è_¸ P¸ P¸ PèaF 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1±Pèaèù|¹] è%_¸ P¸
P¸ Pè*aLThe instruction takes 27 to 39 clocks to execute, and restores the entire±Pè0aè|¹] è»^¸ P¸ P¸ PèÀ` flag register from the stack.±Pèõ`èT|¹] è^¸ P¸ P¸ Pè `LNow, to make life a little easier, the V20/V30 will allow you to call native±Pè`èê{¹] è^¸ P¸ P¸ Pè`Lmode routines from emulation mode just as if they were interrupt servicing±Pè!`è{¹] è¬]¸ P¸ P¸ Pè±_Droutines. This is accomplished with the CALLN and RETI instructions.±Pè¿_è {¹ èJ]èøf PCèn|é å]à è5`0¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLCALLN allows you to call native mode V20/V30 interrupt service routines from±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dL8080 emulation mode, and then return to 8080 mode with the RETI instruction.±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLThis instruction works in a manner very similar to the BRK instruction in±PèTdè³¹] èßa¸ P¸ P¸ PèäcLthat it pushes the PS, PC and PSW onto the stack, except that it sets a MODE±PèêcèI¹] èua¸ P¸ P¸ PèzcLvalue of 1 instead of 0, putting the CPU in native mode. It then vectors to±Pècèß~¹] è a¸ P¸ P¸ Pèc@the code pointed to by the imm8 vector and executes the routine.±Pè"cè~¹] è`¸ P¸ P¸ Pè²b5The opcodes for the RETEM instruction are as follows:±PèÏbè.~¹] èZ`¸ P¸ P¸ Pè_bF Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±PèkbèÊ}¹] èö_¸ P¸
P¸ PèûaI ----------------------------------------------------------------------±Pèbèc}¹] è_¸ P¸ P¸ PèaFimm8 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1±Pè aèÿ|¹] è+_¸ P¸
P¸ Pè0aLThe instruction takes 38 to 58 clocks to execute, and affects no flag as±Pè6aè|¹] èÁ^¸ P¸ P¸ PèÆ`Hit pushes them all onto the stack, to be popped by the RETI instruction.±PèÐ`è/|¹] è[^¸ P¸ P¸ Pè``LThis instruction would come in very handy to implement a CP/M environment in±Pèf`èÅ{¹] èñ]¸ P¸ P¸ Pèö_La V20/V30 machine, but with all the BIOS service routines written in V20/V30±Pèü_è[{¹] è]¸ P¸ P¸ Pè_Linstructions. Put it all in ROM, stick it in the PC`s ROM extra socket, etc.±Pè_èñz¹ è ]èËf PCèA|é å]à è5`¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLRETI is the instruction used to return from interrupt service routines to±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLnormal processing, but it is also used to return from a call made from 8080±Pè¾dè ¹] èIb¸ P¸ P¸ PèNdLemulation mode to a native mode routine. It does its job in the same manner±PèTdè³¹] èßa¸ P¸ P¸ PèäcLin both instances, but since the MODE flag was pushed with a value of 0 when±PèêcèI¹] èua¸ P¸ P¸ PèzcLCALLN was issued, the CPU is set in 8080 mode. It pops the PS, PC and PSW±Pècèß~¹] è a¸ P¸ P¸ PècLfrom the stack, and continues execution in whatever mode it returns in. The±Pècèu~¹] è¡`¸ P¸ P¸ Pè¦b instruction takes no operands.±PèÚbè9~¹] èe`¸ P¸ P¸ Pèjb3The opcode for the RETEM instruction is as follows:±Pèbèè}¹] è`¸ P¸
P¸ PèbF Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0±Pè%bè}¹] è°_¸ P¸ P¸ PèµaI ----------------------------------------------------------------------±Pè¾aè }¹] èI_¸ P¸ P¸ PèNaF 1 1 0 0 1 1 1 1 - - - - - - - -±PèZaè¹|¹] èå^¸ P¸ P¸ Pèê`LThe instruction takes 38 to 58 clocks to execute, and affects all flag as±Pèð`èO|¹] è{^¸ P¸ P¸ Pè`"it pops them all out of the stack.±Pè°`è|¹ è;^èég PCè_}é å]à è5`ÿ¬UìUé èU¹ è&c謹] è c¸ P¸ P¸ Pè"eLThis completes this tutorial. As you can see, the V20 and V30 are extremely±Pè(eè¹] è³b¸ P¸ P¸ Pè¸dLversatile devices, with enhanced and unique instructions that should prove±Pè¾dè ¹] èIb¸ P¸ P¸ PèNd5to be very useful to many programmers and developers.±Pèkdèʹ] èöa¸ P¸ P¸ PèûcLIf you would like to obtain your very own V20 or V30, you may order yours±Pèdè`¹] èa¸ P¸ P¸ Pèc:for $50 plus $1.50 shipping and handling, from us here at:±Pè©cè¹] è4a¸ P¸ P¸ Pè9c3 Micro Consulting Associates±PèXcè·~¹] èã`¸ P¸ P¸ Pèèb3 200-1/2 E. Balboa Boulevard±Pècèf~¹] è`¸ P¸
P¸ Pèb, Post Office Box 4296±Pè½bè ~¹] èH`¸ P¸ P¸ PèMb5 Balboa, California 92661-4296±PèjbèÉ}¹] èõ_¸ P¸
P¸ PèúaLChecks or money orders only, please. No CODs. Please allow 2 weeks for all±Pè bè_}¹] è_¸ P¸ P¸ PèaLpersonal checks to clear if they are from out of state. California residents±Pèaèõ|¹] è!_¸ P¸ P¸ Pè&aLplease add 6% ($3.00) state tax. You will receive the CPU of your choice,±Pè,aè|¹] è·^¸ P¸ P¸ Pè¼`Leither 5- or 8-mhz V20 or V30 (8088- and 8086-compatible, respectively), a±PèÂ`è!|¹] èM^¸ P¸ P¸ PèR`Lcopy of the NEC Preliminary Specifications, an installation manual for your±PèX`è·{¹] èã]¸ P¸ P¸ Pèè_Ltype of computer, a receipt for your records, and full money-back guarantee±Pèî_èM{¹] èy]¸ P¸ P¸ Pè~_Lif for some reason you are not satisfied with your purchase, unless you±Pè_èãz¹] è]¸ P¸ P¸ Pè_Jhappen to destroy or otherwise abuse the chip through improper handling...±Pè _è{z¹] è§\¸ P¸ P¸ Pè¬^;Thank you for taking the time to view this tutorial... Bye.±PèÃ^è"z¹ èN\èüe PCèr{é å]Ã
Very nice! Thank you for this wonderful archive. I wonder why I found it only now. Long live the BBS file archives!
This is so awesome! 😀 I’d be cool if you could download an entire archive of this at once, though.
But one thing that puzzles me is the “mtswslnkmcjklsdlsbdmMICROSOFT” string. There is an article about it here. It is definitely worth a read: http://www.os2museum.com/wp/mtswslnk/