Category : System Diagnostics for your computer
Archive   : DMASLO.ZIP
Filename : DMASLO.C

/* Program a DMA channel for block transfers in verify mode
* in order to steal bus cycles from the CPU, thus decreasing
* execution speed even with interrupts disabled.
*
* Compiled with Microsoft C V5.1
*/

/*
Terry Bohning
12/8/88
Compuserve [71036,1066]
GEnie T.BOHNING

Copyrighô (c© Terrù Bohninç 1988¬ 1989® Aìì rightó reserved.

!!!!!!!!!!!!!!!!!!!!!!!!!!¡ WARNINÇ !!!!¡!!!!!!!!!!!!!!!!!!!!!!
Thió  worë  ió  Copyrighô (c© Terrù Bohninç 1988¬  198¹  anä  alì 
rightó  arå reserved® Thió worë maù bå freelù distributeä iî  aî 
unmodifieä  forí  aó lonç aó saiä distributioî ió  noô  performeä 
witè thå intenô oæ monetarù gain®

É  herebù absolvå myselæ oæ alì blamå iî thå evenô oæ anù  direcô 
oò consequentiaì damagå oò losó whicè maù resulô froí uså oæ  thå 
program®   THÅ USEÒ OÆ THÅ PROGRAÍ ANÄ THÅ INFORMATIOÎ  CONTAINEÄ 
HEREIÎ  BEARÓ FULÌ RESPONSIBILITÙ FOÒ ANÙ ANÄ  ALÌ  CONSEQUENCES¡ 
Iæ  yoõ dï noô understanä whaô thió prograí doeó oò havå noô  haä 
iô explaineä bù someonå whï does¬ DON'Ô USÅ IT!

Thió   prograí   reprogramó  thå  DMÁ  (Direcô   Memorù   Access© 
controller® Iô haó beeî testeä oî ONÅ machine® Iæ yoõ feeì eveî 
slightlù  uncomfortablå abouô this¬ DON'Ô USÅ IT¡ Iæ yoõ dï  uså 
it¬  rebootinç youò machinå beforå doinç anù  subsequenô  seriouó 
worë ió STRONGLÙ recommended.
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*/


#include
#include
#include

#define ERR 0xFF

/*********************** DMA DEFINES *******************/
/* DMA I/O addresses
*/
#define DMA_BASE 0x00
#define STAT_REG 0x08
#define CMD_REG 0x08
#define SNGL_MASK_REG 0x0A
#define MODE_REG 0x0B
#define CLR_BYTE_PTR 0x0C
#define MASTER_CLEAR 0x0D
#define CLR_MASK_REG 0x0E
#define ALL_MASK_REG 0x0F

/* Mask register bits.
*/
#define CH_ON 0x00
#define CH_OFF 0x04

/* ch request bit in status register
* and TC bit
*/
#define Ch_req(ch) (0x10 << (ch))
#define TC(ch) (0x01 << (ch))

/* MODE REG BITS
*/
#define READ_XFER 0x08
#define VERIFY_XFER 0x00
#define AUTO_INIT 0x10

#define DEMAND 0x00
#define SINGLE 0x40
#define BLOCK 0x80

/* Word count and base address regs
*/
#define Ba_reg( ch ) ( (ch) << 1 )
#define Wc_reg( ch ) ( (Ba_reg(ch)) + 1 )

/* Command Register
*/
#define CTLR_DISABLE 0x04
#define DREQ_HI 0x00
#define DREQ_LO 0x40

unsigned int Channel;
unsigned int Count;
unsigned int Polarity;

main(argc, argv)
int argc;
char *argv[]; {
char *cptr;

puts("\nDMASLO Copyright (c) Terry Bohning 1988, 1989. All rights reserved.\n");

/* Argument checking.
*/
if ( (argc == 3 ) || (argc == 4) ){

if ( (Channel = legal_ch(argv[1]) ) == ERR) {
printf("Illegal Channel: %s\n", argv[1]);
usexit();
}

if (argc == 3) {

/* DMASLO channel off
*/
if ( !strcmp( argv[2], "off")
|| !strcmp( argv[2], "OFF")
|| !strcmp( argv[2], "Off")
) {
dmaoff();
exit(0);
} else {
printf("Illegal: %s\n", argv[2]);
usexit();
}

} else {
/* DMASLO channel polarity count
*/
Polarity = ( argv[2][0] - '0');
if ( (Polarity > 1) || (argv[2][1]) ) {
printf("Illegal Polarity: %s\n", argv[2]);
usexit();
}

/* check count
*/
Count = 0;
for( cptr = argv[3]; *cptr; ++cptr ) {
if ( !isdigit(*cptr) ) {
printf("Illegal Count: %s\n", argv[3]);
usexit();
}
Count *= 10;
Count += (*cptr - '0');
}

dmaslo();
exit(0);
}
} else {
usexit();
}
}
/* Reprogram DMA channel to standard parameters.
* From AT Technical Reference.
*/
dmaoff() {
_disable(); /* no interrupts */

/* All channels masked
*/
outp( ALL_MASK_REG, 0x0F);

/* normal sense polarities and otherwise as the
* AT BIOS does at startup.
*/
outp( CMD_REG, 0 );

/* Single Mode, Verify, etc.
* Just as AT BIOS does.
*/
outp( MODE_REG, 0x40 | Channel );

_enable(); /* ints back on */

printf("DMA Channel %d Restored\n", Channel);
}
/* Reprog DMA channel for Read, Block, Verify Mode
* Also reprog DREQ sense if necessary.
*/
dmaslo() {
int i;

_disable(); /* no interrupts */

/* All channels masked
*/
outp( ALL_MASK_REG, 0x0F); /* all channels masked */

/* program polarity
* and check that it will work.
*/
outp( CMD_REG, Polarity ? DREQ_HI : DREQ_LO );

if ( (inp(STAT_REG) & Ch_req(Channel)) == 0 ) {
printf("Polarity %d will not work for Channel %d\n",
Polarity, Channel);

puts("Refer to DMASLO.DOC.");

/* restore normal polarity
*/
outp( CMD_REG, 0 );

_enable();
return;
}

/* Now set up the Mode Register.
*/
outp( MODE_REG, BLOCK | AUTO_INIT | VERIFY_XFER | Channel );

/* Load the Block Count
* DMAC does one more than programmed for.
*/
outp( CLR_BYTE_PTR, 0 ); /* clear byte pointer */
outp( Wc_reg(Channel), (Count-1) & 0xFF ); /* low byte */
outp( Wc_reg(Channel), (Count-1) >> 8 ); /* high byte */

/* Let 'er rip
*/
outp( SNGL_MASK_REG, CH_ON | Channel );

_enable(); /* ints back on */

printf("DMA Channel %d programmed for %d byte Block Verify Transfers\n",
Channel, Count);
puts("Checking for proper operation...");

/* Check for proper operation (should see TC's for this channel).
*/
inp( STAT_REG ); /* clear any latched TC */

for( i = 0; i < 1000; ++i ) {
if ( inp(STAT_REG) & TC(Channel) ) {
puts("Operation Verified");
return;
}
}

puts("DMA not operating.");
puts("Possibly defective DMA controller.");
puts("Try another channel and/or polarity.");

dmaoff(); /* restore to normal */
}
/* check for OK channel number
* return binary of legal channel, else ERR.
*/
legal_ch( chptr )
char *chptr; {
if (chptr[1]) {
return(ERR);
}
switch (*chptr) {
case '0':
case '1':
case '3':
return( *chptr - '0' );
default:
return(ERR);
}
}
/* usage error
*/
usexit() {
puts("Please read DMASLO.DOC for proper usage.");
exit(1);
}
/**************************** EOF **********************/